View CXD4016R_4459634.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Transmission Digital Signal Processor IC for Infrared Spatial Digital Audio Communication
CXD4016R
Description
The CXD4016R is an IC that processes the transmitted digital signals used for infrared spatial digital audio communication (based on the IEC61603-8-1 standard) in consumer products. This IC contains the digital-toanalog converter (DAC) and a PLL circuit for RF signal. RF signal is processed by digital signal processing, so the operation is stable without any adjustments.
Features
Performs all the transmitted digital signal processing on a single chip Supports the infrared spatial digital audio communication system formats for consumer uses Support the three audio sampling frequencies (32kHz, 44.1kHz, 48kHz) Direct output of RF signals enabled by on-chip DAC External RAM and PLL circuit not required
< Audio I/F Block >
Interfaces for various audio ADCs
< Parity Generator Block >
Automatic generation of Reed-Solomon parity for the infrared spatial digital audio communication system format
< Modulator Block >
Digital processing throughout enables the transmitted RF signals in the infrared spatial digital audio communication system formats to be processed directly External analog circuit can be simplified by on-chip digital filter and on-chip DAC for RF signal applications Generation of subcarrier processed digitally
< Controller Block >
Simple pin setting mode Serial interface provided by serial bus
< PLL Block >
On-chip analog PLL circuit for generating the clock signals (640fs) required by the infrared spatial digital audio communication system formats
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E03Z16D64
CXD4016R
Package
64 pin LQFP (Plastic)
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings
Supply voltage Input voltage Output voltage Storage temperature VDD VI VO Tstg - 0.5 to + 3.0 - 0.5 to VDD + 0.5 ( 3.0V) - 0.5 to VDD + 0.5 ( 3.0V) - 55 to + 125 V V V
C
Recommended Operating Conditions
Supply voltage D/A supply voltage PLL supply voltage Operating temperature Sampling frequency precision VDD VDA VPLL Topr 2.5 0.2 2.5 0.2 2.5 0.2 - 40 to + 85 Within 0.1% V V V
C
Input/Output Capacitance
Input capacitance Output capacitance Input/Output capacitance CIN COUT CI/O 16 (max.) 16 (max.) 16 (max.) pF pF pF
Note) Measurement conditions : Tj = 25C, VDD = VI = 0V, f = 1MHz
-2-
CXD4016R
Block Diagram
APCPO APVGS PLVAR PLREF
36 37 41 42 43
APS
44 APAVD PLL OSCI 57 OSCO 59 CK12 53 XRST 64 LRCK 49 BCK 50 DTIN 48 BCKOUT 51 LRCKOUT 52 3 IFEXMD 4 IIFSEL1 5 IIFSEL0 6 EXCKSEL 7 CHNM_BL Controller 8 DIVCODE 9 PCMID 10 EMPIN 14 XSCEN 13 SCLK 15 SWDT 16 CSOD Audio I/F ReedSolomon Parity Generator D/A Converter 21 DAAOUT 22 DAAVD 23 DAAVS 24 DAVREF 25 DAVRO Buffer RAM Modulator Clock Generator Clock Selector 45 APAVS 38 APX
46 VCOT
12 20 27 40 55 58 VSS VSS VSS VSS VSS VSS
11 19 26 39 56 VDD VDD VDD VDD VDD
* Test pins not shown.
-3-
CXD4016R
Pin Configuration
DT2_INF
APCPO
APVGS
APAVD
APAVS
PLVAR
PLREF
TEST7
TEST6 34
48
47
46
45
44
43
42
41
40
39
38
37
36
35
33
LRCK BCK BCKOUT LRCKOUT CK12 CSST VSS VDD OSCI VSS OSCO XTCK4 XSM MST XTST XRST
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
TEST5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCOT
DTIN
APS
APX
VDD
VSS
TEST4 TEST3 TEST2 TEST1 TEST0 VSS VDD DAVRO DAVREF DAAVS DAAVD DAAOUT VSS VDD DACK DAPD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TESTMD
SMCK
EXCKSEL
CHNM_BL
DIVCODE
IFEXMD
IIFSEL1
IIFSEL0
PCMID
EMPIN
XSCEN
-4-
SWDT
CSOD
SCLK
VDD
VSS
CXD4016R
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Symbol TESTMD SMCK IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN VDD VSS SCLK XSCEN SWDT CSOD DAPD DACK VDD VSS DAAOUT DAAVD DAAVS DAVREF DAVRO VDD VSS TEST0 TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 PLREF
I/O I I I I I I I I I I -- -- I I I O O O -- -- O -- -- I I/O -- -- O O O O O O O O O
Description Test mode selector, normally fixed "L". SCAN test pin, normally fixed "H". IIF extension mode. (L : Normal mode, H : Extension mode) Audio input mode selection. Audio input mode selection. Clock selection for modulation. (L : APX internal connection, H : VCOT pin input) Half-band : Channel number selection. (L : 0ch, H : 1ch) Full-band : Bit length control. (L : Full bit, H : 16-bit limited) Full/Half-band mode selection. (L : Full-band, H : Half-band) Source_info pcm_id input, normally fixed "L". (L : PCM data) Source_info emphasis input, (L : No emphasis, H : Emphasis) Digital power supply. Digital GND. Serial interface data clock input. Serial interface enable input (negative logic). Serial interface data write input. Chapter start delay output. Test pin. Test pin. Digital power supply. Digital GND. RF DAC output. Analog power supply for RF DAC. Analog GND for RF DAC. RF DAC reference voltage input, apply 1.1V (typ.) RF DAC internal current setting. Digital power supply. Digital GND. Test output pin. Test output pin. Test output pin. Test output pin. Test output pin. Test output pin. Test output pin. Test output pin. PLL reference output.
-5-
CXD4016R
Pin No. 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
Symbol PLVAR APX VDD VSS APS APVGS APCPO APAVD APAVS VCOT DT2_INF DTIN LRCK BCK BCKOUT LRCKOUT CK12 CSST VSS VDD OSCI VSS OSCO XTCK4 XSM MST XTST XRST
I/O O O -- -- I -- O -- -- I I I I I O O O I -- -- I O I I I I I
Description PLL frequency-divided output (APX output or VCOT input divided by 640). PLL VCO output, 640fs. Digital power supply. Digital GND. PLL reset pin. PLL guard band GND. PLL charge pump output. PLL power supply. PLL GND. External clock input for modulation. Test pin, normally fixed "L". Audio data input. LR clock input. Bit clock input. Bit clock output (3.072MHz). LR clock output (48kHz). Frequency-divided clock output for master clock (12.288MHz). Test pin, normally fixed "L". Digital GND. Digital power supply. Crystal oscillator circuit input for master clock (24.576MHz). Digital GND. Crystal oscillator circuit output for master clock (24.576MHz). Test pin, normally fixed "L". Test pin for SCAN, normally fixed "H". Test pin for SCAN, normally fixed "L". Test pin for SCAN, normally fixed "H". Asynchronous reset input. While power supply is "ON", be sure to reset by fixing "L" after power supply is stabilized.
-6-
CXD4016R
Electrical Characteristics
1. DC characteristics (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item High level input voltage Low level input voltage Symbol VIH VIL IOH = - 100A IOL = 100A VOH = VDD - 0.4V VOL = 0.4V Conditions Min. 1.7 - 0.3 VDD - 0.2 0 - 4.0 4.0 -- 2.3 Typ. -- -- -- -- -- -- -- 2.5 500 2.3 1.05 Between DAVRO and DAAVS VREF = 1.10V, RREF = 2.7k Full-scale Zero-scale LSB-scale Between DAAOUT and DAAVS VDD = 2.5V fs = 44.1kHz Full-band mode V (DAAVD) = 2.5V fs = 44.1kHz Full-band mode V (APAVD) = 2.5V fs = 44.1kHz Full-band mode 2.4 2.5 1.10 2.7 2.7 1.15 Max. VDD + 0.3 0.7 VDD 0.2 -- -- 5 2.7
*2
Unit
Applicable pins
*1
High level output voltage VOH Low level output voltage VOL High level output current IOH Low level output current Input leakage current PLL supply voltage PLL charge pump output current DAC supply voltage DAC reference voltage DAC full-scale adjusting resistor IOL IL VPLL ICPO VDA VREF RREF
V
*2
mA A V A V V k
*2 *1 *3 *4 *5 *6 *7
DAC output current
IDAC
4.67 0
5.194 2 20.3 150 12
5.71 20 160
mA A A mA
*8
DAC load resistance Supply current of digital block Supply current of D/A block Supply current of PLL block Applicable pins
*1
RL IDD
*8
*9
IDA
6.5
mA
*5
IPLL
3.5
mA
*3
*2
*3 *4 *5 *6 *7 *8 *9
TESTMD, SMCK, IFEXMD, IIFSEL1, IIFSEL0, EXCKSEL, CHNM_BL, DIVCODE, PCMID, EMPIN, SCLK, XSCEN, SWDT, APS, VCOT, DT2_INF, DTIN, LRCK, BCK, CSST, XTCK4, XSM, MST, XTST, XRST CSOD, DAPD, DACK, TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7, PLREF, PLVAR, APX, BCKOUT, LRCKOUT, CK12 APAVD APCPO DAAVD DAVREF DAVRO DAAOUT VDD (Pins 11, 19, 26, 39, 56)
-7-
CXD4016R
2. AC characteristics (1) OSCI, OSCO pins (a) When using self-excited oscillation (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Oscillation frequency Symbol fSYS Min. -- Typ. 24.576 Max. -- Unit MHz
(b) When inputting pulses to OSCI (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Pulse frequency High level pulse width Low level pulse width Rise time/fall time Symbol fSYS tWHX tWLX tR, tF Min. 24.330 -- -- Typ. 24.576 20.345 20.345 Max. 24.600 -- -- 2 Unit MHz ns ns ns
tCX (1/fSYS) tWHX tWLX VIH VIH x 0.9 OSCI VDD/2 VIH x 0.1 VIL tR tF
(2)
VCOT pin (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Symbol fCXR tWHXS tWLXR Min. 20.275 0.45 x tCXR 0.45 x tCXR Typ. -- -- -- Max. 31.027 0.55 x tCXR 0.55 x tCXR Unit MHz ns ns
Pulse frequency High level pulse width Low level pulse width
tCXR (1/fCXR) tWHXR tWLXR VIH VIH x 0.9 VCOT VDD/2 VIH x 0.1 VIL tR tF
-8-
CXD4016R
(3)
SCLK, XSCEN, SWDT, SRDT pins (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Symbol tCW tCWH tCWL tCSWH tCSS tCSH tWSU tWHD Min. 200 100 100 170 0 100 20 100 Typ. -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns
Clock period Clock pulse width, high Clock pulse width, low Enable signal pulse width Enable signal setup time Enable signal hold time SWDT Setup time SWDT Hold time
tCW tCSS XSCEN tCWL tCWH tCSH tCSWH
SCLK tWSU tWHD
SWDT
An example of data read phase
(4)
CSOD pin (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Symbol tCSOD Min. 260 Typ. -- Max. -- Unit s
CSOD pulse width
CSOD tCSOD
(5)
XRST pin (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Symbol tXRST Min. 100.0 Typ. -- Max. -- Unit ns
XRST pulse width
XRST tXRST
-9-
CXD4016R
(6)
BCK, DTIN, LRCK pins (VDD = 2.5 0.2V, VSS = 0V, Topr = - 40 to + 85C) Item Symbol tDTS tDTH tLRSK Min. 10 100 -- Typ. -- -- -- Max. -- -- 20 Unit ns ns ns
DTIN setup time DTIN hold time LRCK skew time
BCK tDTS DTIN tLRSK LRCK tDTH
VDD/2
VDD/2
VDD/2
- 10 -
CXD4016R
Description of Functions
Description of clock generator
1. This LSI chip can generate the system clock pulse by connecting a 24.576MHz crystal oscillator to the OSCI pin and OSCO pin. Also, it incorporates 1M (typ.) feedback resistor between the OSCI and OSCO pins. 2. It functions as the system clock by inputting a 24.576MHz external oscillation clock pulse to the OSCI pin while keeping the OSCO pin open. 3. Please keep the frequency precision for system clock within 24.576MHz 100ppm.
Description of PLL circuit
1. In addition to supplying the system clock pulse using the OSCI pin, this LSI requires the modulation clock pulse which is provided by the PLL circuit. The PLL circuit provided on the LSI chip can be used for this purpose. 2. If the sampling frequency of the digital audio input signals is fs, then the modulation clock pulse provided by the PLL circuit has a frequency of 640fs. 3. When the PLL circuit on the LSI is used, input a low level to the EXCKSEL pin and VCOT pin. Furthermore, an external lag-lead filter must be connected to the LSI for the charge pump current output APCPO pin of the PLL circuit. Ensure that the wiring involved is kept as short as possible. 4. When the PLL circuit on the LSI is not used, the LSI chip must be provided with an external PLL circuit. Input a high level to the EXCKSEL pin and the modulation clock pulse to the VCOT pin. The reference signal of the PLL circuit for generating the clock pulses is output to the PLREF pin, and its frequency is set to fs. At this time, the frequency of the clock pulse which has been input to the VCOT pin is divided by 640 inside the LSI, and the pulse with the resulting frequency is output to the PLVAR pin.
Pin setting/serial data interface
The setting modes of this LSI can be broadly classified into two : the pin setting mode and the serial data interface mode. By setting serial data interface mode, switching between pin setting mode and serial data interface mode is enabled. For example, setting SCEN01 bit to "0" validate pin setting mode and setting it to "1" validate serial data interface setting mode during Address 01 in serial data interface mode. (See "(3) Serial setting command table" on the next page.) Followings are pins which can be set even in the serial data interface mode. EXCKSEL pin, DIVCODE pin, CHNM_BL pin, IFEXMD pin, IIFSEL1 pin, IIFSEL0 pin, PCMID pin, EMPIN pin.
- 11 -
CXD4016R
Description of serial data interface
1. Serial data interface timings This LSI enables the various LSI operations to be changed by the SCLK pin, SWDT pin and XSCEN pin. The interface timing chart for each code group is presented below. Also, the SCLK pin should not be used with other devices. Normal communication cannot be performed. 2. XRST pin All the internal registers are initialized to "Default value" presented in the "Serial data interface setting command table" when reset by setting the XRST pin to low.
XSCEN
SCLK
SWDT
A7
A6
A5
A4
A3
A2
A1
A0 Dn - 1 Dn - 2 Dn - 3
D2
D3
D2
D1
D0
Internal registers
Valid
3. Method for disabling the CXD4016R's FSLOCK signal The LRCK input to the CXD4016R must be a stable clock with no jitter. A PLL that uses LRCK as the reference is formed inside the CXD4016R, and this PLL generates a 640fs clock. However, the signal (FSLOCK) that indicates the PLL lock status is generated inside this LSI, and RF generation is temporarily stopped when the lock is lost. This lock detection logic has strict conditions, so if the LRCK jitter is large, the jitter of the clock generated by the PLL is also large, and the lock may be judged as lost. Using a LRCK with large jitter is not recommended, but when a LRCK with large jitter must be used, this LSI has a test mode that can reduce the RF generation stoppage frequency by disabling the FSLOCK signal as follows. FSLOCK can be enabled or disabled by sending the command indicated in the Serial Setting Command Table. At the default setting, FSLOCK operates according to the lock detection logic. To forcibly set the FSLOCK status, send address 71h and data 0Fh by the serial setting command. In addition, to return to the default setting, send address 71h and data 03h by the serial setting command. Performing this process is highly recommended.
- 12 -
CXD4016R
4. Serial setting command table Address (HEX) Default value Length [bit] Signal name SCEN01 EXCKSEL DIVCODE 01h 00h 8 CHNM_BL IFEXMD IIFSEL1 IIFSEL0 res. SCEN02 CRC_FLG VALID_FLG 02h 40h 8 PCM_ID CPRGT_FLG EMPHASIS res. 03h 69h 8 CATEGORY res. FSLOCK_EN 71h 03h 8 FSLOCK res. 1 2 Signal length [bit] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 8 4 1 Value 0 1 0 1 0 1 0 1 0 1 -- -- 0 0 1 0 1 0 1 0 1 0 1 0 1 00 -- 0000 0 1 0 1 11 Effect Invalidate serial setting of Address 01. Validate serial setting of Address 01. APX internal connection. VCOT pin input. Full-band mode. Half-band mode. 0ch/full-bit. 1ch/16-bit limited. Normal mode. Extension mode. Audio input interface mode select 1. Audio input interface mode select 0. Be sure to set the value to "0". Invalidate serial setting mode of Address 02. Validate serial setting mode of Address 02. CRC off. CRC on (default). Source_block is error free. Source_block contains some errors. Data is Linear PCM. Data is used for other purposes. Copyright is asserted. No copyright is asserted. No emphasis. Emphasis. Reserved. Source_info Byte 3 category codes. Be sure to set the value to "0000". Invalidate serial setting mode of FSLOCK. Validate serial setting mode of FSLOCK. Set to unlocked logic forcibly. Set to locked logic forcibly. Be sure to set the value to "11".
- 13 -
CXD4016R
Description of audio I/F
1. As shown below, the audio ADC can be directly coupled in this LSI. DTIN : BCK : LRCK : Connect the data output from ADC Connect the bit clock output from ADC (64fs) Connect the sample clock output from ADC (fs)
The sampling frequencies (fs) which can correspond to this LSI are 32kHz, 44.1kHz, 48kHz. Also, the precision of fs is within 1000ppm. If it gets beyond this range even for a second, the normal operation might not be performed. So care should be taken. 2. This LSI has the LRCKOUT pin, BCKOUT pin and CK12 pin in order to use the audio ADC into which sample clock and bit clock are required to be input. LRCKOUT pin : BCKOUT pin : CK12 pin : sample clock (48kHz) bit clock (48kHz x 64) master clock (12.288MHz (48kHz x 256) )
Connect the LRCKOUT pin to the sample clock of ADC and the LRCK pin of this LSI. And connect the BCKOUT pin to the bit clock pin of ADC and the BCK pin of this LSI. 3. Sixty-four BCK cycles are contained in one LRCK cycle. 4. The DTIN input format can be changed by the setting of resistor with address 01h, or the IFEXMD pin, IIFSEL1 pin and IIFSEL0 pin. Name of iif_mode mode-0 mode-1 mode-2 mode-3 mode-4 mode-5 Note) 1. 2. IFEXMD 0 0 0 0 1 1 IIFSEL [1 : 0] 00 01 10 11 00 01 Data input format MSB first, Left Justified 24 bits I2S 24 bits LSB first, Right Justified 24 bits MSB first, Right Justified 24 bits MSB first, Right Justified 20 bits MSB first, Right Justified 16 bits
When CHNM_BL is set to "1" by the CHNM_BL pin or address 01h of serial data interface, only high-order 16 bits are validated during Full-band mode. Only high-order 16 bits are validated during Half-band mode.
- 14 -
CXD4016R
Timing charts covering what has been described above are presented below.
Audio ADC interface timing charts
LRCK BCK DAOUT MSB LSB Left channel
mode-0
LRCK BCK DAOUT MSB LSB Left channel
mode-1
LRCK BCK DAOUT LSB MSB Left channel
mode-2
LRCK BCK DAOUT MSB LSB Left channel
mode-3
LRCK BCK DAOUT MSB LSB Left channel
mode-4
LRCK BCK DAOUT MSB LSB Left channel
mode-5
- 15 -
C1 R1 2.5VA 2.5VD C2 Rx
Application Circuit
Reset circuit 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
VSS VDD DTIN VCOT APS APX TEST7 TEST6 APAVS PLVAR PLREF TEST5
Audio 50 BCK 51 BCKOUT 52 LRCKOUT 53 CK12 54 CSST 55 VSS 56 VDD 57 OSCI 58 VSS 59 OSCO 60 XTCK4 61 XSM 62 MST 63 XTST
TESTMD
DT2_INF
APCPO
APVGS
49 LRCK TEST4 TEST3 31 TEST2 30 TEST1 29 TEST0 28 VSS 27 VDD 26 RREF DAVRO 25 DAVREF 24 DAAVS 23 DAAVD 22 DAAOUT 21 VSS 20 VDD 19 DACK 18
EMPIN
APAVD
32
C1 = 0.1F R1 = 2.2k C2 = 4700pF Rx = 4.7M
A/D converter
VSS
SCLK
XSCEN
SWDT
SMCK
IFEXMD
IIFSEL1
IIFSEL0
EXCKSEL
CHNM_BL
DIVCODE
PCMID
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
VDD
CXD4016R
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
CSOD
- 16 64 XRST DAPD
1.1V reference voltage
X'tal 24.576MHz
2.5VA
LPF RL
RF output
17
CXD4016R
Notes on Operation
The loop filter portion of the PLL block is important for the characteristics. Therefore, the loop filter should be located as close to the IC pin as possible and surrounded by AGND. In addition, temperature compensation parts should be used for the loop filter capacitor and resistor. The CXD4016R generates a delay during transmission. Labeling the sampling frequency as fs, the delay time is 192/fs [s] in full-band mode. For example, when fs = 48kHz, the delay time is 4ms. In addition, in halfband mode the delay time is 384/fs [s]. In this case for example, when fs = 48kHz, the delay time is 8ms. Note that a delay is also generated during reception by the receive side IC CXD4017R. See the CXD4017R data sheet for details.
CXD4016R Evaluation Board
Description
The CXD4016R evaluation board is a dedicated board designed to allow easy evaluation of the CXD4016R which was developed for transmission of infrared spatial digital audio communication. Optical digital and analog (pin jack) circuits are mounted, and can be switched by a switch. The input audio signal is converted to an infrared spatial digital audio communication system format RF signal by the CXD4016R, and output from a SMB connector.
Features
Supply voltage : + 5V single power supply Analog and optical digital audio input can be selected
Operating Conditions
Supply voltage : + 5V (typ.) Current consumption : 150mA (typ.) Input signal : Analog or optical digital audio signal
Operation Method
The CXD4016R evaluation board allows easy evaluation simply by providing the power supply and inputting an analog or optical digital audio signal. The evaluation procedure is as follows. 1. Connect the power supply to the power supply connection pin J5. 2. SW1 is the manual reset switch. A reset is applied automatically during power-on, but this switch is used to perform reset manually. 3. The DIVCODE pin can be set by DIP switch S2-1. The DIVCODE pin is set low when this switch is OFF, and high when ON. 4. The CHNM_BL pin can be set by DIP switch S2-2. The CHNM_BL pin is set low when this switch is OFF, and high when ON. 5. The IFEXMD pin can be set by DIP switch S2-4. The IFEXMD pin is set low when this switch is OFF, and high when ON 6. The IIFSEL1 pin can be set by DIP switch S2-5. The IIFSEL1 pin is set low when this switch is OFF, and high when ON. 7. The IIFSEL0 pin can be set by DIP switch S2-6. The IIFSEL0 pin is set low when this switch is OFF, and high when ON. 8. The audio signal can be selected by DIP switch S2-7. The optical digital audio signal is selected when this switch is OFF, and the analog audio signal when ON. 9. Connect the optical digital audio signal to the U8 square optical connector. 10. Connect the analog audio signal to the J1 pin jack.
- 17 -
CXD4016R
11. When the analog audio signal is selected, the sampling frequency can be changed by DIP switch S2-8. 48kHz is set when this switch is OFF, and 44.1kHz when ON. 12. Always set DIP switches other than noted above to OFF. The above contents are listed in the tables below for reference. S1 1 2 3 4 5 6 7 8 Mode Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF Always OFF
S2 1 2 3 4 5 6 7 8
Mode OFF : DIVCODE = L, ON : DIVCODE = H OFF : CHNM_BL = L, ON : CHNM_BL = H Always OFF OFF : IFEXMD = L, ON : IFEXMD = H OFF : IIFSEL1 = L, ON : IIFSEL1 = H OFF : IIFSEL0 = L, ON : IIFSEL0 = H OFF : Optical digital, ON : Analog OFF : 48kHz, ON : 44.1kHz (only when the analog audio signal is selected)
13. Light emitting diode D1 is off when DIVCODE is low, and lighted when DIVCODE is high. 14. Light emitting diode D2 is off when CHNM_BL is low, and lighted when CHNM_BL is high. 15. Light emitting diodes D3 and D4 indicate the sampling frequency of the audio signal. This relationship is shown in the table below. D3, D4 Off, off Off, lighted Lighted, lighted Flashing, flashing Sampling frequency 44.1kHz 48kHz 32kHz Unlock
16. Light emitting diodes D5 to D8 are not used. 17. The infrared spatial digital audio communication system format RF signal is output from SMB connector J8. 18. J2 and J3 are not used.
- 18 -
CXD4016R
CXD4016R EVB Semiconductor Parts List
Parts No. U1, 3 U2 U4, 21 U5 U6 U7 U8 U9 U10 U11 U12 U13, 14, 15, 16, 17, 18 U19, 20 U22 Q1 D1, 2 D3, 4 D5, 6 D7, 8 D9 to 20 Product name NJM2100M AK5353VT TC74LCX541F CXD4016R TC74VHC04F CS8415A-CZ TORX141P FXO-31FL 24.576MHz EP1K100QI208-2 EPC2LI20 FXO-31FL 22.5792MHz LM317A TL7705CP AD8057ART 2SC2223L TLG124 TLY124 TLO124 TLR124 1S1588 Manufacturer New Japan Radio Asahi Kasei Microsystems Toshiba SONY Toshiba Cirrus Logic Toshiba Kyocera Kinseki ALTERA ALTERA Kyocera Kinseki National Semiconductor Texas Instruments Analog Devices NEC Toshiba Toshiba Toshiba Toshiba Toshiba
FPGA Operation
1. Selects the optical digital audio signal or the analog audio signal selected by S2-7. 2. Converts the selected audio signal to the DTIN pin input format set by S2-4, S2-5 and S2-6. 3. Detects the sampling frequency.
- 19 -
Circuit Diagram
AIF
PLD1 CXD4016R
SDTO_1 LRCK_AD MCLK SCLK_AD PDN
(High-speed Signal)
SDTO_1 LRCK_AD MCLK SCLK_AD PDN
DIF
(High-speed Signal)
(High-speed Signal)
- 20 ORIG RMCK SCLK XSCEN DAPD SWDT
(High-speed Signal)
COPY EMPH RST RERR RCBL PRO CHS NVERR OSCLK OLRCK SDOUT AUDIO U C ORIG RMCK
(Middle-speed Signal)
COPY EMPH RST RERR RCBL PRO CHS NVERR OSCLK OLRCK SDOUT AUDIO U C SCLK XSCEN DAPD SWDT DAAOUT
DT2_INF DTIN LRCK APS_XRST BCK BCKOUT LRCKOUT CSOD CK12 CSST XRST IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN
DT2_INF DTIN LRCK APS_XRST BCK BCKOUT LRCKOUT CSOD CK12 CSST XRST IFEXMD IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL DIVCODE PCMID EMPIN
RFOUT
DAAOUT
PWXRST XRSTPW1 XRSTPW2 XRSTPW2 XRSTPW1
POWER
CXD4016R
CXD4016R EVB circuit diagram (TOP)
VA5
C1 22/16V R1 20k AINL1 TP1 LC-2S-W
1
7
C2 0.1 R2 10k AINR1 TP2 LC-2S-R VD5
1
A A
A
8
C3 22/16V
1 5
R3 20k R4 10k
4
6
2
R7 330k U1B NJM2100M
A
1
VA5 C4 4.7/16V T C5 2200p R9 10k U2 C6 4.7/16V T C7 0.1
A
3
R5 330
R6 470
DGND TP3 LC-2S-BK
R8 4.7k
U1A NJM2100M
D
J1 RCA JACK 2P
A
Rch_1 (RED)
3
Lch_1 (WHITE) C10 4.7/16V T
A
2
3
RV1A 50k
C8 22/16V
C9 0.1
R10 4.7k
2
1
A
A
A
1
C11 0.1 C12 10/16V T C13 0.1
A
A
VA5 R11 20k R12 10k
A
1 2 3 4 5 6 7 8 AINR AINL VREF VCOM AGND VA VD DGND AK5353VT TST TTL DIF PDN SCLK MCLK LRCK SDTO
16 15 14 13 12 11 10 9
6
5 1 5 7 6
C16 22/16V
A
R13 20k R14 10k
4
RV1B 50k R15 330 C17 4.7/16V T C20 2200p
A
2
8
4
R17 330k U3B NJM2100M AGND TP5 LC-2S-BK
1
A
R18 4.7k
U3A NJM2100M
C18 10/16V T
C19 0.1
D
1
A
A
A
A
1
- 21 VA5 R16 470 VD5
C14 22/16V
C15 0.1
A
A
D
MCLK TP4 LC-2S-Y
VA5
3
R19 100 SDTO_1
A
C21 22/16V
C22 0.1
SCLK TP6 LC-2S-G R21 R22 R23 R24
U4
R20 4.7k
11 12 100 13 100 14 22 15 100 16 17 18 19 20
Y8 GND Y7 A8 Y6 A7 Y5 A6 Y4 A5 Y3 A4 Y2 A3 A2 Y1 G2 A1 VCC G1
10 9 8 7 6 5 4 3 2 1 TC74LCX541F VD33 C23 0.1
D
PDN SCLK_AD MCLK LRCK_AD
CXD4016R EVB Circuit Diagram (AUDIO)
CXD4016R
R25 2.2k
1
PLVAR TP7 LC-2S-BL
1
PLREF TP8 LC-2S-Y
R26 4.7M C25 0.1
C24 4700p
A
APS TP9 LC-2S-Y
D
APX TP10 LC-2S-Y
1
APS_XRST DT2_INF TP11 LC-2S-BL R27 22 C26 0.1 C27 0.1
A A
VA25P R28 0 R29 0 VD25D R30 100 R31 100
DTIN TP12 LC-2S-Y
1
DT2_INF DTIN
1
48
47
46
45
44
43
42
41
40
39
38
1 37
36
35
34
33
VSS
VDD
DTIN
VCOT
APS
APX
TEST7
TEST6
APAVS
APAVD
1
1
1
1
APCPO
APVGS
PLVAR
PLREF
TEST5
LRCKOUT BCKOUT TP13 TP14 LC-2S-G LC-2S-BL
LRCK BCK TP16 TP15 LC-2S-Y LC-2S-Y
TP17 LC-2S-BK AGND
TP18 LC-2S-BK DGND
1
DT2_INF
LRCK 50 BCK BCKOUT LRCKOUT CK12 CSST VSS U5 VDD CXD4016R OSCI VSS OSCO XTCK4 XSM MST XTST XRST DAVREF DAAVS DAAVD DAAOUT VSS VDD DACK DAPD DAVRO 25 24 23 22 21 20 19 18 17
1 1
49 LRCK TEST3 TEST2 TEST1 TEST0 VSS VDD 26 27 28 C28 0.1 29 30 31 TEST4
32
A D
BCK R32 R33 22 54
1
BCKOUT 100 53 52
100
51
LRCKOUT
VA25A
CK12 TP20 LC-2S-Y 55 56 57 Y1 59 C33 27pF 61 62 63 64 R37 is missing number. 60 58 C29 0.1
R34
CSST CSST
1
CK12
R36 2.7k
A
C30 18p
1
2
3
VA25D
A
1
CX-49G_24.576MHz
C31 0.1
A
R39 150 R40 0
1
TESTMD
SMCK
IFEXMD
IIFSEL1
IIFSEL0
EXCKSEL
CHNM_BL
DIVCODE
PCMID
EMPIN
VDD
VSS
SCLK
XSCEN
SWDT
CSOD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
IFEXMD TP25 LC-2S-Y
1 1
IIFSEL1 IIFSEL0 EXCKSEL TP26 TP27 TP28 LC-2S-G LC-2S-G LC-2S-BL
16
1
1
IFEXMD
C37 0.1
IIFSEL1
R43 100
1 1 1 1
D
C38 0.01 DAAOUT CSOD TP30 LC-2S-G SCLK TP31 LC-2S-Y XSCEN TP32 LC-2S-Y
A A
IIFSEL0
EXCKSEL
CHNM_BL
R44 10k
R45 1k
DIVCODE
PCMID
1 1 1
EMPIN
SWDT TP33 LC-2S-Y
1
SCLK
TP34 TP35 TP36 TP37 EMPIN PCMID DIVCODE CHNM_BL LC-2S-BL LC-2S-BL LC-2S-Y LC-2S-Y
CXD4016R
CXD4016R EVB Circuit Diagram (MAIN)
XSCEN
SWDT
CSOD
1
- 22 TP23 DAPD LC-2S-Y
TP19 LC-2S-BL
DAVREF TP21 LC-2S-G
R35 1.2k
VR1 200
C34 0.1
C32 DAAOUT 0.1 TP22 LC-2S-Y
A
R38 910
A
VA5 DAPD R41 0 TP24 DACK LC-2S-Y C36 0.01 R42 4.7k
VA5
XRST
C35 0.1
A
Q1 2SC2223L
DAAOUT_Buf TP29 LC-2S-Y
1
D
D
VD33 VD33 VD33
D
U6 R47 100 COPY EMPH C42 0.01 VA5
D A
D
C39 0.1 C40 0.01 U7
D
SPDIF TP38 LC-2S-Y R46 47k
D
1
1 2 3 4 5 6 7 R48 47k
D
1A 1Y 2A 2Y 3A 3Y GND C41 0.01 R51 47k R55 R59 R49 100
VCC 6A 6Y 5A 5Y 4A 4Y
14 13 12 11 10 9 8
ORIG C U R50 100 R53 100 R57 100 R60 100 100 100
D
74VHC04F
D
VD33 R52 R54 R56 R58 0 100 100 22
L1 47H CS8415A-CZ
RST RMCK RERR RCBL PRO CHS R61 1.2k C43 0.1 C44 1000p C45 4700p C47 0.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 COPY VL2+ EMPH RXP0 RXN0 VA+ AGND FILT RSTx RMCK RERR RCBL PRO CHS ORIG VL3+ C U H/S VL+ DGND DGND2 DGND3 AUDIOx SDOUT OLRCK OSCLK NVERR
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AUDIO SDOUT OLRCK OSCLK NVERR
1
1
A D
- 23 A A
U8
OUT GND VCC NC NC
1 2 3 4 5
TORX141P
C46 0.1
D
AGND TP39 LC-2S-BK
DGND TP40 LC-2S-BK
CXD4016R EVB Circuit Diagram (DIGITAL INTERFACE)
CXD4016R
J2 VD33 U9
22
4
VDD OUT
3
IFdata10 VD25B IFdata9 IFdata8 IFdata7 IFdata6
IFdata10
IFdata9
IFdata8
IFdata7
IFdata6
IFdata5
IFdata4
IFdata3
IFdata2
R62
D
FXO-31FL_24.576MHz
D
IFdata1
C48 0.1
1
INHX
GND
2
10 9 8 7 6 5 4 3 2 1
GND A9 GND A7 GND A5 GND A3 GND A1 IL-10P-S3EN2
D
TH1 TH TH6 TH VD33 VD33 R64 1k R63 10k IFdata5 IFdata4 IFdata3 IFdata2 IFdata1 C54 0.1 C49 0.1 C50 0.1 C51 0.1 C52 0.1
TH2 TH
TH3 TH
TH4 TH
TH5 TH
R8 R7 R6 R5 R4 R3 R2 R1 COM
9 8 7 6 5 4 3 2 1
RA1 M9-1-103J
J3 10 9 8 7 6 5 4 3 2 1
TP41 TP43 TP44L TP42 LC-2S-G LC-2S-Y LC-2S-BL C-2S-Y SCLK_AD MCLK LRCK_AD SDTO1
nCS CS nWS IFdata10 nRS IFdata9 I_O VCCINT IFdata8 I_O IFdata7 I_O IFdata6 I_O VCCIO I_O I_O I_O I_O I_O GND I_O DEV_OE VCCINT Ded_Input CRYST24M Ded_Input GND DEV_CLRn I_O VCCIO I_O I_O I_O IFdata5 I_O IFdata4 GND IFdata3 I_O IFdata2 IFdata1 DATA7 VCCIO DATA6 I_O DATA5 DATA4 I_O DATA3 DATA2 DATA1
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
GND A9 GND A7 GND A5 GND A3 GND A1
1
1
1
1
R67 C55 0.1
100
R65 R66 R68
100 100 100
DT2_INF DTIN LRCK R71 R72 0 100
LRCK_AD MCLK
R69
22
R70
100
TH7 TH
RA2 M9-1-103J
SCLK_AD PDN
R73
100
APS_XRST BCK BCKOUT LRCKOUT CSOD
COPY C57 0.1
C56 0.1
1
CK12 R74 R76 100 100 CSST XRST IFEXMD
C58 0.1 U10 EP1K100QI208-2_1
D
1
R8 R7 R6 R5 R4 R3 R2 R1 COM
SDTO_1
C53 0.1
9 8 7 6 5 4 3 2 1
IL-10P-S3EN2
D
TP45 LC-2S-BK DGND
TP46 LC-2S-BK DGND
D
EMPH RST RERR RCBL PRO
R75
100
C59 0.1
1
1
1
I_O I_O LED1 LED2 LED3 LED4 GND DSW1_1 DSW1_2 LOCK DSW1_3 I_O DSW1_4 VCCIO DSW1_5 DSW1_6 DSW1_7 DSW1_8 RMCK VCCINT CRYST22M I_O GL_CLK1 GND VCC_CKLK Ded_Input GlobalCLK1 Ded_Input GND_CLK GND LED5 VCCIO LED6 I_O LED7 LED8 I_O DSW2_1 VCCINT DSW2_2 I_O DSW2_3 I_O DSW2_4 DSW2_5 VCCIO I_O DSW2_6 I_O DSW2_7 I_O DSW2_8
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
COM R1 R2 R3 R4
U11 TH13 TH R82 10k
TH12 TH TH14 TH C68 0.1 R81 C73 22 0.1 RMCK
1
3 2 1 20 19
DSW2_1 DSW2_2 DSW2_3 DSW2_4 DSW2_5 DSW2_6 DSW2_7 DSW2_8
LED1 LED2 LED3 LED4
C69 0.1
C70 0.1
C71 0.1
C72 0.1
TH15 TH
RA4
4 5 6 7 8
DCLK VCCSEL NC NC OE
TCK DATA TDO VCC TMS
VD33 18 VPP 17 NC 16 NC 15 NC 14 VppSel
1 2 3 4 5
LED5
LED6
LED7 LED8
DSW2_1
DSW2_2
DSW2_3
DSW2_4
DSW2_5
DSW2_6
DSW2_7
DSW2_8
nCS GND TDI nCASC nInt_Conf
100 LED1
100 LED2
100 LED3
100 LED4
100 LED5
100 LED6
100 LED7
9 10 11 12 13
LC-2S-Y TP50 RMCK XRSTPW2 U12
3 2
100 LED8
R87
R88
R89
R83
R84
R85
R86
D1
D2
D3
D4
D5
D6
D7
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
M9-1-103J
D
D
M9-1-103J ON VD25B
OUT ON GND
VDD INHX
4 1
A6E-8104 S1
C76 0.1 FXO-31FL_22.5792MHz
D
D8
R8 R7 R6 R5 R4 R3 R2 R1 COM
9 8 7 6 5 4 3 2 1
RA5 R8 R7 R6 R5 R4 R3 R2 R1 COM 9 8 7 6 5 4 3 2 1
R90
STA_5 TLO124
STA_6 TLO124
STA_7 TLR124
16 15 14 13 12 11 10 9
FULL/HALF TLG124A
Fs_1 TLY124
Fs_0 TLY124
16 15 14 13 12 11 10 9
CHNM_BL TLG124A
D
CXD4016R
CXD4016R EVB Circuit Diagram (PLD)
STA_8 TLR124
- 24 D
CHS NVERR
R77
100
SDOUT LC-2S-BL TP47
OLRCK LC-2S-G TP48
OSCLK LC-2S-Y TP49
C60 0.1
IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL C61 0.1 TH9 TH C63 0.1 R78 R79 R80 C65 0.1 C67 0.1 100 100 100 DIVCODE PCMID
OSCLK OLRCK
C62 0.1
SDOUT
AUDIO
TH8 TH TH10 TH
U C
C64 0.1
EMPIN SCLK XSCEN DAPD SWDT
ORIG
TH11 TH
C66 0.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 TCK CONF_DONE nCEO TDO VCCIO GND SDTO_1 I_O LRCK_AD CLKUSR_I_O MCLK I_O SCLK_AD I_O PDN RDYnBUSY I_O COPY INIT_DONE GND VCCINT VCCIO GND EMPHx RSTx RERR RCBL PRO I_O CHS NVERR GND VCCINT VCCIO GND OSCLK OLRCK I_O SDOUT I_O AUDIOx VCCIO GND U C I_O ORIG VCCINT GND TMS TRST nSTATUS DATA0 DCLK nCE TDI VCCINT GND DT2_INF DTIN LRCK USER_IO VCCIO GND APS_XRST BCK BCKOUT I_O LRCKOUT CSOD VCCIO GND CK12 I_O CSST I_O XRST IFEXMD VCCINT GND IIFSEL1 IIFSEL0 EXCKSEL CHNM_BL VCCINT GND DIVCODE I_O PCMID I_O VCCIO GND EMPIN SCLK I_O XSCEN DAPD SWDT VCCIO GND MSEL0 MSEL1 VCCINT nCONFIG
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
RA3 M5-1-102J VD33 XRSTPW1 VD33
C74 0.1 C75 0.1 EPC2LI20
D
1 2 3 TCK GND 4 5 TDO Vcc 6 7 TMS NC 8 NC NC 10 9 TDI GND J4 XG4C-1031 R91 1k VD33
D
D
D
VD25B
A6E-8104 S2 VD25B
VD25B
TP51 LC-2S-R +5V
1
L2 SN3-200
VD5
J5
C77 22/16V
C78 0.1
C79 0.1
C80 47/16V
1 2
D
D
IL-2P-S3EN2
JP1
L3 SN3-200
VA5
A
D
C81 0.1
C82 47/16V
TP52 TP53 LC-2S-BK LC-2S-BK AGND AGND
A
A
1
A
1
A
D9 1S1588 VD25B VD25D U15
3
1
1
U13 U14
3
LM317A LM317A VOUT
2
D2.5V_B TP54 LC-2S-G RM1 0 RM2 0 VIN D2.5V_D TP55 LC-2S-G L5 SN3-200
D10 1S1588
D1 1S15881 LM317A
2
VA25P
1
3
VIN
VOUT
2
L4 SN3-200
A2.5V_P TP56 L6 LC-2S-O SN3-200
RM3 0
VIN VOUT
ADJ
ADJ
1
1
R92 240 D13 1S1588 C91 47/16V
D D D D
C83 0.1 R93 240 C92 0.1
D D
C84 47/16V
3
C85 0.1
C86 47/16V
ADJ
R94 240
1
D14 1S1588 C93 47/16V
2
D12 1S1588 C89 47/16V
2
C90 0.1 VR3 500 R96 270
A
C94 0.1
3
C87 0.1
A
C88 47/16V
A
1
1
R98 750 R99 750 R102 270
A A
A
R100 750
1
1
1
D3.3V TP57 L7 LC-2S-R SN3-200 VD33 RM4 0 U17
3
3
VIN VOUT
2
VIN VOUT
2
A2.5V_D TP58 LC-2S-O L8 SN3-200
RM5 0
3
VIN VOUT
2
A2.5V_A TP59 LC-2S-O L9 SN3-200
1
ADJ
ADJ
ADJ
1
1
3
3
D 2
D
A A A
A 2
3
C104 47/16V VR6 500 R107 270
1
C105 0.1
C106 47/16V C111 10/16V
A
C107 0.1
1
1
R111 270 R109 750 R113 270
A A
R112 100
R110 750
A
1
- 25 C96 10/16V D16 1S1588 LM317A VA25D C98 0.1 R105 240 C99 47/16V D19 1S1588 C100 0.1 C101 47/16V
2
3
VR2 500
R95 270
C95 10/16V
D
D
VR4 500
R97 270
C97 10/16V
A
A
A
R101 270
R103 270
A A
A
A
D15 1S1588
D17 1S1588 U18 LM317A
VA25A RM6 0 R106 240 C102 0.1 D20 1S1588 C108 47/16V VR7 500 R108 270 C112 10/16V
A
U16
LM317A
R104 240
D18 1S1588
C103 47/16V C109 0.1
A A A A
2
VR5 50
C110 10/16V
D
D
R114 270
A A
A
CXD4016R
CXD4016R EVB Circuit Diagram (POWER)
VD5
1
VD5 XRSTPW1 TP60 LC-2S-Y
VD5
VD5
VD5
R115 10k C113 0.1 R116 10k C115 0.1 U21 R118 10k C118 4.7/16V T td = 60ms XRSTPW1 XRSTPW2 C119 0.1 VD25B 1 2 3 4
D
U19
C114 0.1 VCC VsSENSE RESET RESET 8 7 6 5
D
R117 10k
XRSTPW2 TP61 LC-2S-Y
1
SW1 AB-15AH
1 2 3 4
Vref RESIN Ct GND
8 VCC 7 VsSENSE 6 RESET 5 RESET
U20 Vref RESIN Ct GND
TL7705CP
TL7705CP R119 10k
1
2
3
- 26 TC74LCX541F
D
C116 4.7/16V T
C117 0.1
td = 60ms
D
1 2 3 4 5 6 7 8 9 10 G1 VCC A1 G2 A2 Y1 A3 Y2 Y3 A4 A5 Y4 A6 Y5 A7 Y6 A8 Y7 GND Y8
D
20 19 18 17 16 15 14 13 12 11
CXD4016R EVB Circuit Diagram (RESET)
CXD4016R
TP62 LC-2S-BK AGND
1
Emitter Voltage Source
A
VA5
J6 1 2 C120 0.1 IL-2P-S3EN2
A A
1 OUT C122 3p VCC 5 2 VEE IN+ AD8057ART IN- 4 3 VA5
A
U22
2
C121 3p
3
L10 68H (Large Size)
1
TP64 LC-2S-BK AGND
VR8 10k
TP63 LC-2S-Y TX_LED C123 0.1
J7 F-CONNECTOR NF-R-2
1
1
A
R121 2.2k R123 0 C126 2200p
R120 1k C124 0.1 C125 2200p
2
A
3
1
- 27 C129 120p C130 10p VR9 10k
A A 2 A
1
R122 300
L11 6.8H
L12 12H
DAAOUT
A
R124 75 R125 2.2k
J8 SMB RF OUT
C127 27p
C128 120p
A A A
A
A
CXD4016R EVB Circuit Diagram (RFOUT)
CXD4016R
CXD4016R
Pattern Diagram
CXD4016R EVB A Side Pattern Diagram
CXD4016R EVB B Side Pattern Diagram
- 28 -
CXD4016R
CXD4016R EVB GND Layer Pattern Diagram
CXD4016R EVB Power Supply Layer Pattern Diagram
- 29 -
CXD4016R
CXD4016R EVB A Side Silk Diagram
CXD4016R EVB B Side Silk Diagram
- 30 -
CXD4016R
Package Outline
(Unit : mm)
64PIN LQFP (PLASTIC)
12.0 0.2 10.0 0.1 + 0.2 1.5 - 0.1
48
33
49
32
A 64 17
1
0.5
16 b
0.08 M
0.08 S S
0.25
0.1 0.1
0.20 0.05
0.5 0.2 0.6 0.15
0 to 8 DETAIL A
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE JEITA CODE JEDEC CODE LQFP-64P-L023 P-LQFP64-10X10-0.5 TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS EPOXY RESIN SOLDER PLATING 42 ALLOY 0.32g
LEAD PLATING SPECIFICATIONS ITEM LEAD MATERIAL SOLDER COMPOSITION PLATING THICKNESS SPEC. 42 ALLOY Sn-2%Bi 5-20m
- 31 -
0.145 0.055
Sony Corporation

▲Up To Search▲

Price & Availability of CXD4016R

	To Download CXD4016R Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .